The present invention relates to a method of inspecting a circuit pattern of a semiconductor device for defects and analyzing defects to determine the causes of defects by using a charged particle beam, a system for inspecting a circuit pattern of a semiconductor device and analyzing defects, and circuit pattern inspecting system.
Circuit pattern miniaturization and increase in the layers of multilevel structures have made a rapid progress and new process techniques have been introduced to cope with the progressively increasing level of integration of semiconductor devices, such as semiconductor storage devices and semiconductor integrated arithmetic elements. Such a rapid progress of circuit pattern miniaturization and increase in the layers of multilevel structures have entailed a serious problem associated with the reduction of the yield of semiconductor devices by defects in the lower layers of semiconductor devices formed on a semiconductor wafer.
FIG. 2 is a fragmentary sectional view of a portion of a semiconductor device 11 near the surface of the semiconductor device 11 in a process of fabricating the semiconductor device 11. A lower wiring layer 22 is electrically connected to an upper wiring layer by a plug 21 formed in a via extending through an insulating film covering the lower wiring layer 22. It is possible that the electrical connection of the lower wiring layer 22 to the upper wiring layer is prevented by the residual insulating film remaining between the plug 21 and the layer 22. When forming gate electrodes 23, a conductive substance of the same electrical conductivity as the gate electrodes 23 is formed around the gate electrodes 23, and it is possible that the gate electrode 23 and the plug 21 are short-circuited or the lower wiring layer 22 is short-circuited by the conductive substance.
A conventional inspecting apparatus using reflected light has difficulty in detecting such internal defects in semiconductor devices. Therefore, a semiconductor device inspecting and defect analyzing procedure represented by a flow chart shown in FIG. 3 is executed. It is difficult to detect defects in circuit patterns of semiconductor devices formed on a semiconductor wafer in a circuit pattern forming step of a semiconductor device fabricating process. After the completion of formation of circuit patterns of semiconductor devices on a semiconductor wafer in step 30, the semiconductor wafer is subjected to a probe test for testing the electrical functions of the semiconductor devices in step 31 before dicing the semiconductor wafer into chips. If the semiconductor devices a re memory chips, all the bits of the memory chips are inspected to classify the bits into good ones and defective ones. A fail bit map indicating the coordinates of the defective bits is made in step 32. A defective chip is cut out of the semiconductor wafer, surface layers of the semiconductor device formed on the chip are removed by etching to expose a layer presumed to have defects on the basis of data provided by the fail bit map in step 33. A presumably defective portion of the exposed layer is observed under a scanning electron microscope in step 34 to look deep into the causes of the defects.
Another procedure slices longitudinally a defective portion of the chip cut out of the semiconductor wafer to prepare a sample for section observation in step 35, and observes the section of the defective portion under a transmission electron microscope or a scanning transmission electron microscope to look deep into the causes of defects in step 36. However, since defects and their positions are detected by the probe test in step 31 after the completion of the circuit, it takes, in some cases, several months to complete investigation for determining the causes of the defects, and the fabrication of products at low yield is continued until the causes of the defects are determined and hence the conventional semiconductor device inspecting methods causes immeasurable economical loss.
Accordingly, it is an object of the present invention to provide a method of inspecting circuit patterns of semiconductor devices for defects and analyzing defects to find causes of defects, a system for inspecting circuit patterns of semiconductor devices and analyzing defects, and a circuit pattern inspecting system capable of detecting defects in the circuit patterns formed on a semiconductor wafer by a circuit pattern forming step during the circuit pattern forming step, of facilitating the extraction and observation of defective portions from the semiconductor wafer, of accurately analyzing the causes of defects and of reducing the time necessary to achieve the determination of the causes of the defects and to take measures to eliminate the causes of the defects.
With the foregoing object in view, the present invention provides a method of inspecting circuit patterns formed on a semiconductor wafer for defects and analyzing the defects, including the steps of detecting locating defects by using a charge particle beam, such as an electron beam, finding a chip having defects on the basis of positions of the defects located by using the charged particle beam, extracting a chip having the defects from the semiconductor wafer, processing the extracted chip to prepare a thin sample, observing the thin sample under a transmission electron microscope (hereinafter abbreviated to xe2x80x9cTEMxe2x80x9d) or a scanning transmission electron microscope (hereinafter abbreviated to xe2x80x9cSTEMxe2x80x9d) to determine the causes of the defects.
Since the circuit patterns are inspected for defects by using a wafer inspecting apparatus that uses an electron beam and is capable of changing electron beam current and deceleration voltage, defects in the internal structures of a semiconductor device that cannot be detected through the observation of the surface of the semiconductor wafer can be detected.
Positions of defects or portions near defects are marked, coordinates of the positions of defects are accurately determined or the distance between a reference point on the circuit pattern and positions of defects are measured to facilitate the confirmation of the positions of the detected defects in the subsequent steps.
Morphologies of defects.can be easily known through the observation of the sample having the defects under a TEM or a STEM and hence the causes of the defects can be quickly determined.
Since defects can be detected during the step of forming the circuit pattern and the causes of the defects can be determined by the system of the present invention, the detection of defects does not need to wait until the final step in which a probe test is executed, defects can be detected and measures to eliminate the defects can be taken in a short period, so that period necessary to develop a new semiconductor device can be greatly reduced. When mass-producing semiconductor devices, defects can be detected before the final step of the semiconductor device fabricating process. Consequently, period in which defective semiconductor devices are produced can be greatly reduced and the reduction of yield can be prevented.